This application claims priority under 35 U.S.C. xc2xa7xc2xa7119 and/or 365 to 197 36 447.0 filed in Germany on Aug. 21, 1997; the entire content of which is hereby incorporated by reference.
The invention relates to a device and a method for switching input data frames from a plurality of input lines to output data frames on a plurality of output lines. In particular, the device and method are provided for switching data frames which comprise time slots which are divided into several sub-channels. The device and method of the invention can perform an efficient switching of such data frames at an arbitrary rate, i.e. at the normal rate of the time slots or at the sub-rate of the sub-channels.
Such normal rate or sub-rate switching is particularly advantageous in telecommunication networks, in particular in telecommunication networks using PCM-links (Pulse Code Modulation links). Furthermore, the device and method of the invention find wide application for testing and simulation equipment, where data frames need to be switched between a plurality of input lines and a plurality of output lines.
In a given configuration of a telecommunication network, more capacity is demanded, when more subscribers are to be connected without extending the facilities of the telecommunication network. This is particularly true for mobile cellular telecommunication networks where new (mobile) subscribers are added to the network at a fast rate. Each new subscriber can be considered as using a new channel for transmission and reception of information and therefore, the obvious demand is to increase the number of channels whenever a new subscriber is added.
The physical connections in the core of a telecommunication network (e.g. between exchanges and base stations or between base transmitter stations and mobile subscribers) are usually PCM-links (Pulse Code Modulation links) for a frame-based transmission and reception of data. That is, on the PCM-links or PCM-lines data is transmitted in successive frames which are transmitted/received at a fixed frame rate of e.g. 125 xcexcs (8 kHz) (2048 kbits/s). The frame can be subdivided into a certain number of time slots (also called channels), typically 32 or 24 time slots depending on the system type. Each time slot has a capacity to carry information data (i.e. speech data) at a rate of 8 kbit/s which is the normal telephony speech quality. For example, one time slot consists of 8 bits and corresponds to a transmission speed of 64 kbits/s (full rate) on one individual PCM-link, wherein speech is respectively coded as information data of 8 bits in each time slot.
Modern compression/decompression techniques, however, allow to compress/decompress speech data to a smaller number of bits than 8 bits, i.e. to transcode the speech to a lower data rate using a smaller number of bits. Therefore, instead of adding one more complete new channel in the mobile telecommunication system when a new subscriber station is to be connected, a more advantageous and efficient use of the resources in the network is to perform a compression/decompression of the speech data and to subdivide the time slots further into several sub-time slots or sub-channels.
A further aspect that may lead to a subdivision of the time slots into sub-time slots or sub-channels is the transmission of signalling information between modules in the system which also uses time slots on the PCM-links. This signalling information can be transmitted at a lower speed, i.e. with less bits per second, such that the usage of a full time slot for this signalling data would be a waste of resources.
When one time slot e.g. consists of 8 bits and corresponds to a transmission speed of 64 kbits/s (at full rate) on a PCM-link, then using a sub-time slot (sub-channel) of 4 bits will use a corresponding speed of 32 kbits/s (sub-rate) wherein one time slot is divided into two sub-time slots. Similarly a sub-time slot of 1 bit gives a speed of 8 kbits/s and 8 sub-time slots per time slot. If a channel has a bandwidth of n*8 kbits/s with n=1 . . . 7, then n=1 can be called a sub-rate channel with a half rate, n=2 can be called a sub-rate channel with a full rate and 2 less than n less than 8 can be called a sub-rate channel with an enhanced rate. The normal rate (a full channel) channel has 64 kbits/s. Obviously, looking at one PCM-link, the individual frames of a series of frames may each be subdivided differently into sub-channels of different sub-rates.
In the telecommunication networks many exchanges and switching devices are necessary, e.g. to switch input data frames from a plurality of input lines to output data frames on a plurality of output lines. There are well established techniques for full-rate switching, i.e. switching packets or frames having a number (32 or 24) of time slots of equal bandwidth (e.g. 64 kbits/s). However, the technique of using sub-channels with different sub-rates is a fairly recently developed new idea and has put new demands on the hardware in the switching devices, since the old full-rate switching devices in general cannot handle the switching of time slots which are further subdivided into sub-time slots or sub-channels.
Thus, there is the need for developing new switching architectures that do not only handle the normal rate switching but also the sub-rate switching.
SUB-RATE SWITCHING USING A CONVENTIONAL NORMAL RATE SWITCH
FIG. 1 shows a group switch sub-system GSS for switching data frames from one switching network terminal SNT A to a switching network terminal SNT B on input and output lines i1, o1; i2, o2 using a normal rate switch NRS having an add-on sub-rate switch SRS which is to take care of the switching of the sub-channels or sub-time slots.
The sub-rate switch SRS is connected to the normal switch via one or more physical links each containing a number of time slots. The sub-rate switch SRS can connect any bit from any time slot coming from the normal rate switch to any bit in any time slot going back to the normal rate switch NRS.
FIG. 2 shows an example of one time slot in an input data frame IDF and a time slot of an output data frame ODF in a 24 kbits/s sub-rate connection. Using the sub-rate switch extension to the normal rate switch NRS, a connection of a sub-rate channel x from the switching network terminal SNT A to a sub-rate channel y at the switching network terminal SNT B can be established using the following three steps:
1. A 64 kbits/s connection in the normal rate switch from the time slot on SNT A which contains sub-channel x to any free time slot on the sub-rate switch SRS is established.
2. In the normal rate switch NRS, a connection is established from any other free time slot on the sub-rate switch SRS to the time slot on the SNT B containing the sub-channel y.
3. In the sub-rate switch SRS, the connection between the appropriate bits of the bit positions in the time slots that were selected in steps 1 and 2 is made.
FIG. 3 shows a group switch sub-system GSS with a 64 K implementation. The sub-rate switch SRS (consisting of sub-rate switch modules SRSM for each plane) is connected to the normal switch via 8 pairs of time switch modules TSMs to give 4 K multiple positions MPUs. The time switching modules TSMs have the DL2 interfaces replaced by a new interface with 512 time slots, but their switching function is unchanged. RP designates the regional processors and SPM is the space switch module, whereas CLM is the clock module providing the synchronization within the group switch sub-system GSS.
Because the sub-rate switch can connect any time slot to any time slot, the speech memories in the connecting time switching modules TSMs are not needed. For each bit of each outgoing time slot, the sub-rate switch SRS must have one memory location in a control memory. The entry of the control memory location defines a specific bit in a switch pattern memory which should be read. Hence, in order to connect a channel of more than 8 kbits/s a number of control memory locations must be written, too. For example, to set up the 24 kbits/s connection shown in FIG. 2 requires three control memory locations to be written. However, the bits of a sub-channel are thus guaranteed to be in the same order in an output time slot as they were in the input time slot.
As will be appreciated, the time switching modules TSM (in the group switching system GSS) are the time switch modules only for the full-rate channels. The add-on modules SRS and SRSM in FIGS. 1, 3 enable the sub-rate switching. For example, the add-on module SRSM handles 8 PCM-links on the input and 8 PCM-links on the output. Therefore, the SRSM consists of 8 identical base modules (FIG. 3), each handling 8 PCM-links at the input and generating one PCM-link at the output. This requires first to store one frame from all channels and then read out the data in a different order.
The configuration of a sub-rate switch module of FIG. 3 is shown in FIG. 4 with more details. FIG. 4 relates to the preamble features a), b), c) of claim 1 and claim 21. Here, input data frames from a plurality of input lines i1, i2 . . . iN (N=8) are switched to output data frames on a plurality of output lines o1, o2 . . . oM (M=8). In general, Nxe2x89xa0M is valid, however, in the following, the case N=M will be considered. As is seen from FIG. 4, for switching 8 input PCM-links to 8 PCM output links, 64 frame store buffer FSB must be used, each storing one complete frame of the respective input data frames. A first switch pattern memory SPM selects the bit positions to be read in the time slot (i.e. the bits corresponding to a sub-time slot in the time slot) and the second switch pattern memory SPMxe2x80x2 selects the time slot out of the (32 or 24) time slots stored in the respective frame store buffers FSB. As is seen from FIG. 4, the hardware requirements are extensive for such a sub-rate switch. Furthermore, the sub-rate switch module SRSM is limited to 8 PCM-links and depends on the time switching module TSM to switch the sub-rate channels. Sub-rate switching of e.g. 16 PCM-links must use two TSM modules and two SRSM modules. Furthermore, a whole PCM-frame from all 8 incoming PCM-links must be buffered for each of the outgoing PCM-links as FIG. 4 illustrates.
The advantage of using the add-on sub-rate switch to the conventional full-rate switch (FIG. 1) is that the reading of the frame store buffer FSB can be done at the PCM bit rate of typically 2 Mbits/s. However, the hardware requirements are extensive, e.g. for an implementation with 16 PCM-links on the input and 16 PCM-links on the output regarding the circuit board level, two sub-rate switch modules SRSM consist of 16 circuit boards (plus two time switch modules TSM) assuming a standard European printed circuit board of 233xc3x97160 mm2. If the configuration should be increased to more than 16 PCM-links on the input and output, obviously the hardware requirement is even more extensive in the configuration using an additional sub-rate switch to the conventional full-rate switch.
Therefore, the object of the present invention is to provide a switching device and a switching method that perform an efficient fast switching of data frames including full-rate and sub-rate time slots without the need of extensive hardware.
This object is solved by a device for switching input data frames from a plurality of N input lines to output data frames on a plurality of M output lines, comprising:
a) a frame memory for storing input data frames;
b) a switch pattern memory for storing a predetermined switch pattern; and
c) a control means for selecting bits from bit positions in said stored input data frames and for assigning said selected bits to bit positions on output data frames according to said stored predetermined switch pattern;
characterized in that
d) said frame memory comprises a number j=2 to K of frame memories each storing all input data frames of all input lines;
e) said switch pattern memory comprises a number of j=2 to K of switch pattern units each storing a predetermined switch pattern associated with a respective one of said frame memories; and
f) said control means is provided for sequentially selecting a respective number of M/K bits from input data frames stored in a j-th frame memory, with j=1 to K, according to a respective switch pattern stored in an associated j-th switch pattern unit, and for assigning said selected bits to bit positions simultaneously on output data frames on a predetermined output line sub-group including M/K output lines.
Furthermore, this object is solved by a method for switching input data frames from a plurality of N input lines to output data frames on a plurality of M output lines, comprising the following steps:
a) storing input data frames in a frame memory;
b) storing a predetermined switch pattern in a switch pattern memory; and
c) selecting bits from bit positions in said stored input data frames and assigning said selected bits to bit positions on output data frames according to said stored predetermined switch pattern by a control means;
characterized by the following steps:
d) storing all input data frames of all input lines in a number j=2 to K of frame memories;
e) storing a predetermined switch pattern associated with a respective one of said frame memories in a number of j=2 to K of switch pattern units; and
f1) sequentially selecting a respective number of M/K bits from input data frames stored in a j-th frame memory, with j=1 to K; and
f2) simultaneously assigning said selected bits to bit positions on output data frames on a predetermined output line sub-group including M/K output lines according to a respective switch pattern stored in an associated j-th switch pattern unit.
Such a method and such a device are capable of performing a sub-rate switching more economically, essentially utilizing a different buffering technique and a special control logic. Implementation in hardware of the proposed module can be done with a minimum number of standard components. As a comparison, for an implementation of 16 PCM-links on the input and 16 PCM-links on the output, regarding the circuit board level, the inventive device and method only occupies one standard European printed circuit board with no need of additional time switching modules TSM as explained above with reference to FIGS. 1 to 4.
The inventive device and method is essentially based on the concept of using several frame store memories and several switch pattern units parallely and grouping the output lines into a number of sub-groups. The switch pattern units associated with the respective frame memories then respectively assign bits on the output line sub-group simultaneously after having read the respective bit values from bit positions indicated by the switch pattern sequentially.
Advantageously, the sequential selecting of bits from the stored input data frames and the simultaneous assignment of the selected bits to the bit positions on the output data frames on the sub-group of output lines is done at a higher clock rate than the reading-in of bits to the frame store buffers. Thus, it can be ensured that the assigning of bits to all output data frames is performed in a bit- and frame-synchronized manner.
Advantageously, for a system of 16 PCM input links and 16 PCM output links, only two parallely working frame store memories are used together with one switch pattern memory of the same size as before indicated in FIG. 4. The switch pattern memory is only differently divided into switch pattern units respectively for the odd and even switch pattern used for the respective frame store memory. Thus, since only one switch pattern memory and only two frame store memories are used for 16 PCM-links on the input and 16 PCM-links on the output, the hardware requirements are much less than in the add-on sub-rate switch.
A further advantage of the device and method of the invention is that is has a general scaleable switching function with no side effects. The method and device can be implemented in a well-balanced hardware device, where a minimum number of standard components are used and the relaxed timing demands are such that no physical difficulties are expected at the component and board level. The implementation is highly economical in terms of component utilization and production of boards. Thus, due to the division of the switching module into parallelly working units where each unit is working in a time-shared process with a relaxed timing at a faster rate than the PCM bit rate (e.g. 8 times the PCM bit rate in the 16 input/16 output configuration), the sub-rate switching requires less hardware and can still operate at the bit rate of the incoming PCM data frames.
Further advantageous embodiments and improvements of the invention may be taken from the dependent claims. Hereinafter, the invention will be illustrated with reference to its embodiments and with reference to the attached drawings.